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* * * * * * * * *
TE CH
T431616B
SDRAM
FEATURES
+2.7 to +3.6V power supply Dual banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock Burst Read Single-bit Write operation DQM for masking Auto refresh and self refresh 32ms refresh period (2K cycle) MRS cycle with address key programs - CAS Latency ( 1 & 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) Available package type in 50 pin TSOP(II)
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616B is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clockcycle . Range of operating frequencies , programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications.
*
and 60-pin CSP
ORDERING INFORMATION
PART NO. T431616B-20S T431616B-20C T431616B-10S T431616B-10C MAX FREQUENCY 50 MHz 50 MHz 100 MHz 100 MHz PACKAGE TSOP-II CSP TSOP-II CSP
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V DD DQ0 DQ1 V SSQ DQ2 DQ3 V DDQ DQ4 DQ5 V SSQ DQ6 DQ7 V DDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TE CH
T431616B
PIN ARRANGEMENT
(TSOP-II Top View)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Vss DQ15 DQ14 V SSQ DQ13 DQ12 V DDQ DQ11 DQ10 V SSQ DQ9 DQ8 V DDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 Vss 50PINTSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH)
(CSP Bottom View)
VDD A1 A10/AP N.C CS CAS WE N.C DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VDD
7 6
A3 A2 A0 N.C N.C RAS LDQM N.C N.C VSSQ VDDQ DQ4 VSSQ VDDQ DQ0
5 4 3
A4 A5 A7 A9 N.C CLK UDQM N.C N.C VDDQ VSSQ DQ11 VDDQ VSSQ DQ15
2 1
VSS A6 A8 BA CKE N.C N.C N.C DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 VSS
R
P
NM
LK
J
H
G
F
E
D
C
B
A
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TE CH
T431616B
BLOCK DIAGRAM
I/O Control
LWE
Bank Select
Data Input Register
LDQM
Row Decoder
Row Buffeer Refresh Counter
Sense AMP
512K x 16
Output Buffer
DQi
Address Register
CLK
512K x 16
ADD
LRAS
LCBR
Col. Buffer
Column Decoder
Latency & Burst Length
LCKE LRAS LCBR LWE LCAS Timing Register Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
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PIN CLK
CS
TE CH
T431616B
PIN DESCRIPTION
NAME System Clock Chip Select INPUT FUNCTION
Active on the positive going edge to sample all input. Disables or enables device operation by masking or enabling all input except CLK,CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.
A0 ~ A10/AP BA
Address Bank Select Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10,column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Select bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK
RAS
Row Address Strobe with RAS low.
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK
CAS
Column Address Strobe with C A S low.
Enables column access .
WE L(U)DQM DQ0 ~ DQ15 V DD/VSS VDDQ /VSSQ
Write Enable Data Input/Output Mask Data Input/Output Data Output Power/Ground No Connection/Reserved for Future Use
Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins.
Power Supply/Ground Power and gr ound for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
N.C/RFU
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Parameter
TE CH
T431616B
ABSOLUTE MAXIMUM RATINGS
Symbol VIN,VOUT VDD,VDDQ Iout PD TOPR Tstg Value -1.0 to 4.6 -1.0 to 4.6 50 1 -10 to +85 -55 to 125 Unit V V mA W Voltage on Any Pin Relative To Vss Supply Voltage Relative To Vss Short circuit Output Current Power Dissipation Operating Temperature Storage Temperature
C C
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -10 to +85 C , Voltage referenced to VS S=0V)
Parameter Supply Voltage Input High Voltage Input Low Voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD,VDDQ VIH VIL VOH VOL IIL IOL Min. 2.7 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max. 3.6 VDD+0.3V 0.8 0.4 5 5 Unit V V V V V uA uA 1 2 IOH=-2mA IOL=2mA 3 4 Notes
Note : 1. VIH (max) = 4.6V AC for pulse width 10ns acceptable. 2. VIL (min) = -1.0V AC for pulse width 10ns acceptable. 3. Any input 0V VIN VDD+ 0.3V , all other pin are not under test = 0V. 4. Dout = disable , 0V VOUT VDD .
CAPACITANCE
(TA =25C ,VDD =3.3V, f = 1MHz)
Pin CLOCK ADDRESS DQ0 ~ DQ15 RAS,CAS,WE,CS,CKE,LDQM, UDQM Symbol CCLK CADD COUT CIN Min 2.5 2.5 4.0 2.5 Max 4.0 5.0 6.5 5.0 Unit pF pF pF pF
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( One Bank Active)
TE CH
T431616B
DC CHARACTERISTICS
TA = -10 to +85C , VIH(min)/VIL(max)=2.0V/0.8V
Parameter Operating Current ICC1 120 2 mA 2 30 mA 2 10 mA ICC3 PS 10 40 mA 10 140 ICC4 140 Refresh Current Self refresh Current ICC5 ICC6 140 1 mA
CAS Latency 2
Symbol
MAX.
Unit
Test Condition
Burst Length = 1
Note
mA tRCtRC(min) ,tCCtCC(min),IOL= 0 mA
CKE VIL(max),tCC=15ns CKE VIL(max),CLK
1,3
Precharge Standby ICC2 P Current in powerICC2 PS down mode Precharge Standby ICC2 N Current in non power-down mode ICC2 NS Active Standby Current in powerdown mode ICC3 P
VIL(max), tCC =
3
CKE VIH(min), CS VIH(min),tCC=15ns Input signals are changed one time during 30ns CKEVIH(min),CLK
VIL(min),tCC=
3
Input signals are stable CKE VIL(max),tCC=15ns CKE VIL(max),CLK
VIL(max),tCC=
3
Active Standby ICC3 N Current in non power-down mode (One Bank Active) ICC3 NS Operating Current (Burst Mode)
CKEVIH(min), CS VIH(min),tCC=15ns Input signals are changed one time during 30ns CKEVIH(min),CLK
VIL(min),tCC=
3
Input signals are stable CAS Latency 3 IOL=0 mA,Page Burst All Band Activated
1,3
tCCD= tCCD(min) 2,3
mA tRC tRC(min) mA
CKE 0.2V
Note:
1. Measured with output open. Addresses are changed only one time during tCC(min) . 2. Refresh period is 32ms. Addresses are changed only one time during tCC(min) . 3. tCC : Clock cycle time. tRC : Row cycle time. tCCD : Column address to column address delay time.
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TE CH
T431616B
AC OPERATING CONDITIONS
(VDD = +2.7 to +3.6V , TA= -10 to +85 C) Parameter
Input levels (V IH/V IL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
Value
3.0 / 0 1.4
Unit
V V ns V
tr / tf = 1 / 1
1.4 See Fig.2
3.3V 1200 ohm Output VOH(DC)=2.4,IOH=-2mA VOL(DC)=0.4,IOL=2mA 870 ohm 30pf Output ZO=50 ohm
Vtt=1.4v 50 ohm
30pf
(Fig.1) DC Output Load Circuit
(Fig.2)AC Output Load Circuit
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TE CH
T431616B
OPERATING AC PARAMETER
(AC opterating conditions unless otherwise noted) Parameter
Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. Address delay Last data in to row precharge Last data in to burst stop Col. Address to col. Address delay Number of valid output data
Symbol
Speed Version -10 -20
20 20 20 50 100K 70 1 2 1 1 1 1 1 130 40 40 40 80
Unit
ns ns ns ns ns ns CLK CLK CLK CLK ea
Note
1 1 1 1 1 2 2 2 3 4
tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min)
CAS latency=3 CAS latency=2 CAS latency=1
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required
with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL + BL-2 clocks.
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TE CH
T431616B
AC CHARACTERISTICS
(AC opterating conditions unless otherwise noted) Parameter
CAS 3 CLK cycle time CAS 2 CAS 1 CAS 3 CLK to valid CAS Output delay 2 CAS 1 CAS 3 Output data CAS hold time 2 CAS 1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS Latency = 3 CLK to output in CAS Latency = Hi-Z 2 CAS Latency = 1 Latency = Latency = Latency = Latency = Latency = Latency = Latency = Latency = Latency = Symbol
-10
Min Max Min
-20
Max
Unit
Note
10
20 1K 20 40 7 9 20 7 9 14 2.5 2.5 4 8 8 4 2 1 2 2 4 18 18 38 14 14 19 ns ns ns ns ns ns 3 3 3 3 2 ns 2 ns 1 1K ns 1
tCC
10 20 -
tSAC
2.5
tOH
2.5 4
tCH tCL tSS tSH tSLZ
3 3 2.5 1 1 -
tSHZ
-
Note: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns,transient time compensation should be considered, i.e.,[(tr+tf)/2-1]ns should be added to the parameter.
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TE CH
T431616B
(Unit : number of clock)
CAS Latency
3 2 1
FREQUENCY vs. AC PARAMETER RELATIONAHIP TABLE
T431616B-20S
Frequency
50MHz(20.0ns) 50MHz(20.0ns) 25MHz(40.0ns)
tRC
130ns
7 7 4
tRAS
80ns
4 4 2
tRP
40ns
2 2 1
tRRD
40ns
2 2 1
tRCD
40ns
2 2 1
tCCD
20ns
1 1 1
tCDL
20ns
1 1 1
tRDL
40ns
2 2 1
T431616B-10S
Frequency
100MHz(10.0ns) 83MHz(12.0ns) 75MHz(13.0ns) 66MHz(15.0ns) 60MHz(16.7ns)
(Unit : number of clock)
CAS Latency
2 2 2 2 2
tRC
70ns
7 7 6 6 5
tRAS
50ns
5 5 4 4 3
tRP
20ns
2 2 2 2 2
tRRD
20ns
2 2 2 2 2
tRCD
20ns
2 2 2 2 2
tCCD
10ns
1 1 1 1 1
tCDL
10ns
1 1 1 1 1
tRDL
20ns
2 2 2 2 2
Note : 1. Clock count formula : clock
base value (round off whole number). clock period
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11 0 11 x 11 10 0 10 x 10 0 1
TE CH
8 0 1 8 0 0 8 1 0 8 1 1 8 0 0 7 7 v 6 v 6 5 LTMODE 5 v 4 v 4 WT 3 v 3 2 v 2 BL 1 v 1 7 7 6 5 LTMODE 6 5 4 WT 4 3 2 BL 2 1 7 6 5 4 3 2 1 0 JEDEC Standard Test Set (refresh counter test) 0
T431616B
MODE REGISTER
9
9
Burst Read and Single Write (for Write Through Cache)
1 0
9
3
Use in future
0
11 x 11 0
10 x 10 0 x
9
Vender Specific
0
9 0
Mode Register Set
Bit2-0 000 001 010 011 100 101 110 111 0 WT=0 1 2 4 8 R R R Full page Sequential
v = Valid x = Don't care
WT=1 1 2 4 8 R R R R
Burst length
Wrap type
1 Bit6-4 000 001 010 011 100 101 110 111
Interleave CAS Latency R R 2 3 R R R R Remark R : Reserved
Latency mode
Mode Register Write Timing
CLOCK
CKE CS RAS CAS WE
A0-A11
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TE CH
T431616B
Burst Length and Sequence
(Burst of Two)
Starting Address (column address A0 binary) Sequential Addressing Sequence (decimal) Interleave Addressing Sequence (Decimal)
0 1 (Burst of Four)
Starting Address (column address A1-A0 binary)
0,1 1,0
0,1 1,0
Sequential Addressing Sequence (decimal)
Interleave Addressing Sequence (Decimal)
00 01 10 11 (Burst of Eight)
Starting Address (column address A2-A0 binary)
0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2
0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0
Sequential Addressing Seque nce (decimal)
Interleave Addressing Sequence (Decimal)
000 001 010 011 100 101 110 111
1Mx16 divice.
0,1,2,3,4,5,6,7 1,2,3,4,5,6,7,0 2,3,4,5,6,7,0,1 3,4,5,6,7,0,1,2 4,5,6,7,0,1,2,3 5,6,7,0,1,2,3,4 6,7,0,1,2,3,4,5 7,0,1,2,3,4,5,6
0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain CKE = `H' , L(U)DQM = `H' and the other pin are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue mode register set command to initalize the mode register. Cf.) Sequence of 4 & 5 is regardless of the order.
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Register
TE CH
T431616B
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn CS Mode Register Set H X L Auto Refresh Refresh Self Refresh Entry Exit H L H H H H H H L H L H H H X H L H X X X X X L H L H L L H L L L L L H L X H L H L L H X L H H H L X V X X H X V X L H X H L L H H X V X X H X V H H X H H L L L X V X X H X V X X X X X X X X X X X X V X 7 V X L H X V V V X X Row Address L H L H X
Column Address (A0~A7) Column Address (A0~A7)
RAS CAS WE DQM BA A 10/AP A9 ~A0 Note L L L X X 1,2 3 3
Bank Active & Row Address Read Column Address Write & Column Address Burst Stop Bank Selection Both Banks Entry Clock Suspend or Active Power Down Exit Precharge Entry Precharge Power Down Mode DQM No Operation Command Exit
Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4,5 4,5 6 4
H X XX X X L H HH (V=Valid , X=Don't Care , H=Logic High , L=logic Low)
Notes : 1. OP Code : Operation Code. A0 ~A10/AP , BA : Program keys.(@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by `Auto'. Auto / self refresh can be issued only at both banks precharge state. 4. BA : Bank select address. If 'Low' : at read , wriye , row active and precharge , bank A is selected. If `High' : at read , wriye , row active and precharge , bank B is selected. If A10/AP is `High' : at row precharge , BA ignored and both banks are selected. 5. During burst read or write with auto precharge , new read/write command cannotbeissued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data -in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Taiwan Memory Technology, Inc. reserves the right P.13 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
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TE CH
T431616B
tCH
Single Bit READ-Write Cycle (Same Page) @CAS Latency=3,Burst Length=1
0 CLOCK
tCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCC
CKE
HIGH
tRAS tRC
*Note1
tSH
CS
tRCD tSH tSS tRP
RAS
t SS tSH tCCD
CAS
tSS tSH tSS
ADDR
Ra
tSS
*Note2
Ca
Cb
tSH
Cc
Rb
*Note2. 3
*Note2. 3
*Note2. 3
*Note4
*Note2
BA
Bs
Bs
Bs
Bs
Bs
Bs
A10/AP
Ra
*Note3
*Note3
*Note3
*Note4
Rb
tRAC tSRC tSH
DQ
tSLZ
Qa
tOH
Db
tSS tSH
Qc
WE
tSS tSH
DQM
tSS
Row Active
Read
Write
Read Precharge
Row Active
:Don't care
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TE CH
T431616B
*note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA 0 1 Active & Read/Write Bank A Bnak B
3. Enable and dis able auto precharge function are controlled by A10/AP in read/wirte command.
A 10/AP 0 1
BA 0 1 0 1
Operation Disable auto precharge,leave bank A active at end of burst. Disable auto precharge,leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst.
4. A10 /AP and BA control bank precharge when precharge command is asserted. A10 /AP BA 0 0 1 0 1 X precharge Bank A Bank B Both Banks
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CLOCK CKE
TE CH
T431616B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Power Up Sequence
0
High level is necessary
CS tR P
SS
tR C
SS
tR C
SS SS tCCD
RAS
SS
SS
SS SS
CAS
SS
SS
SS SS
ADDR
SS
Key
RAa
SS
SS SS
BA
SS
Key
A10/AP
SS SS
SS SS
Key
RAa
DQ High-Z
SS SS SS
WE
SS
DQM
High level is necessary
Precharge All Banks
Auto Refresh
Auto Refresh
Mode Register Set
(A-Bank) Row Active
:Don't care
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0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read & Write Cycle at Same Bank @Burst Length = 4
1
HIGH
*Note1
tRC
t RCD
RAS
*Note2
CAS
ADDR
Ra
Ca0
Rb
Cb0
BA
A10/AP
Ra
Rb
tOH CL=2 tRAC
*Note3
Qa0 t SAC
Qa1 t OH Qa0
Qa2
Qa3
*Note4
Db0
Db1
Db2
Db3 tRDL
DQ CL=3
*Note3
t SHZ Qa1 Qa2 Qa3
*Note4
Db0
Db1
Db2
Db3 tRDL
tSAC WE
t SHZ
DQM
Row Active (ABank)
Read (ABank)
Precharg e (ABank)
Row Active (A-Bnak)
Write (ABnak)
Precharge (a-Bnak)
:Don't care
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi Z(tSHZ) after the clock. 3. Access time from Row active command.
tCC*(tRCD+CAS latency-1)+tSAC
4. Output will be Hi Z after the end of burst.(1,2,4,8 bit burst)Burst can't end in Full Page Mode. Taiwan Memory Technology, Inc. reserves the right P.17 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
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0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Page Read & Write Cycle at Same Bank @ Burst Length = 4
1
HIGH
tR
CD
RAS
*Note2
t CCD
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
tR
DL
CL=2 DQ CL=3
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
tC
Dd0
Dd1
DL
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd2
WE
*Note3
*Note1
DQM
Row Active (A-Bnak)
Read (ABnak)
Read (ABnak)
Write (ABnak)
Write (ABnak)
Precharge (A-Bnak)
:Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
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0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Page Read Cycle at Different Bank @ Burst Length = 4
1
HIGH
*Note1
RAS
*Note2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
BA
A10/AP
RAa
RBb
CL=2 DQ CL=3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
WE
DQM
Row Active (A-Bank)
Read (ABank) Row Active (B-Bank)
Read (BBank)
Read (ABank)
Read (BBank)
Read (ABank)
Precharge (A-Bank)
:Don't care
*Note : 1. CS can be don't cared when RAS , CAS and WE are high at the clock high going edge. 2. To interrupt a burst resd by row precharge, both the read and the precharge banks must be the same.
Taiwan Memory Technology, Inc. reserves the right P.19 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Page Write cycle at Different Bank @ Burst Length = 4
1
HIGH
CS
RAS
CAS
*Note2
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
BA
A10/AP
RAa
RBb
DQ
DAa0
DAa1
DAa2
DAa3
DBb0
DBb1
DBb2
DBb3
DAc0
DAc1
DBd0
DBd1
t CDL
t RDL
WE
*Note1
DQM
Row Active (A-Bank)
Row Active (B-Bank) Write (ABank)
Write (BBank)
Write (ABank)
Write (BBank)
Precharge (A-Bank)
:Don't care
*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same. Taiwan Memory Technology, Inc. reserves the right P.20 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read & Write Cycle at Different Bank @ Burst Length = 4
1
HIGH
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
BA
A10/AP
RAa
RBb
RAc
*Note1
t CDL CL=2 DQ CL=3
QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2
WE
DQM
Row Active (A-Bank)
Read (ABank)
Row Active (B-Bank)
Precharge (A-Bank)
Write (BBank) Row Active (A-Bank)
Read (ABank)
:Don't care
*Note : 1. tCDL should be met to complete write.
Taiwan Memory Technology, Inc. reserves the right P.21 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read & Write Cycle with Auto Precharge @ Burst Length = 4
1
HIGH
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
BA
A10/AP
Ra
Rb
CL=2 DQ CL=3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
WE
DQM
Row Active (A-Bank)
Row Active (B-Bank) Read with Auto precharge (ABank)
CL=2 Auto Precharge Start Point (A-Bank) CL=3 Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (BBank)
Auto Precharge Start Point (ABank)
:Don't care
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode)
Taiwan Memory Technology, Inc. reserves the right P.22 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Clock suspension & DQM Operation Cycle @ CAS Latency = 2 ,Burst Length = 4
1
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A10/AP
Ra
DQ
Qa0
Qa1
Qa2
Qa3
tSHZ
Qb0
Qb1
t SHZ
Dc0
Dc2
WE
*Note3
DQM
Row Active
Read
Clock Suspension
Read Read QDM
Write Write QDM Clock Suspension
Write QDM
:Don't care
*Note 1. DQM is needed to prevent bus contention.
Taiwan Memory Technology, Inc. reserves the right P.23 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full Page
1
HIGH
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
*Note2
1
1
CL=2 DQ
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
2
2
CL=3
QAa0
QAa1
QAa2
QAa3
QAa4
QAb0
QAb1
QAb2
QAb3
QAb4
QAb5
WE
DQM
Row Active (A-Bank)
Read (ABank)
Burst Stop
Read (ABank)
Precharge (A-Bank)
:Don't care
*Note : 1. Burst can't end in full page mode, so auto precharge can't issue. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the lable 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of `Full Page write burst stop cycle'. 3. Burst stop is valid at every burst length. Taiwan Memory Technology, Inc. reserves the right P.24 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Write Interrupted by Prechareg Command & Write Burst Stop Cycle @ Burst Length=Full Page
1
HIGH
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10/AP
RAa
tBDL
t RDL
*Note3
DQ
DAa0
DAa1
DAa2
DAa3
DAa4
DAb0
DAb1
DAb2
DAb3
DAb4
DAb5
WE
DQM
Row Active (A-Bank)
Write (ABank)
Burst Stop
Write (ABank)
Precharge (A-Bank)
:Don't care
*Note : 1. Burst can't end in full page mode, so auto precharge can't issue. 2. Data -in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. Taiwan Memory Technology, Inc. reserves the right P.25 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Burst Read Single bit Write Cycle @ Burst Length = 2
1
HIGH
RAS
*Note2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
BA
A10/AP
RAa
RBb
RAc
CL=2 DQ CL=3
DAa0
DAb0
DAb1
DBc0
DAd0
DAd1
DAa0
DAb0
DAb1
DBc0
DAd0
DAd1
WE
DQM
Row Active (A-Bank)
Row Active (A-Bank) Write (ARead with Auto Bank) Precharge (ABank)
Row Active (A-Bank)
Write with Auto Precharge (ABank)
Read (ABank)
Precharge (A-Bank)
:Don't care
*Note : 1. BRSW modes is enabled by setting A9 `High' at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to `1' regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycle. Taiwan Memory Technology, Inc. reserves the right P.26 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
CLOCK CKE
TE CH
T431616B
1 2 3
SS SS
*Note2
Active/ Precharge Power Down Mode @ CAS latency = 2, Butsr length = 4
0 4 5 6 7 8 9
SS tss tss
10
11
12
13
14
15
16
17
18
19
tss
*Note1
SS
*Note3
CS
SS SS
SS SS
RAS
SS SS
SS SS
CAS
SS SS
SS SS
SS
SS
ADDR
SS
Ra
SS
Ca
SS
SS SS
BA
SS
SS
SS
A10/AP
SS
Ra
SS tSHZ
DQ
SS
SS
Qa0
Qa1
Qa2
SS
SS SS
WE
SS
SS
SS SS
DQM
SS
Precharge PowerDown Entry
Row Active Precharge Active PowerPowerDown Exit Down Entry
Read Active PowerDown Exit Precharge
:Don't care
*Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK+tSS prior to Row active command. 3. Can not violate minimum refresh specification.(32ms) Taiwan Memory Technology, Inc. reserves the right P.27 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE CS
TE CH
T431616B
2 3 4 5 6
SS SS
*Note2 *Note4
Self Refresh Entry & Exit Cycle
1 7 8 9 10 11 12 13
SS tRCmin
*Note1 *Note3 *Note6
14
15
16
17
18
19
SS
SS tSS SS
*Note5
SS
SS
RAS
SS SS
SS SS
*Note7
CAS
SS SS
SS SS
ADDR
SS SS
SS SS
BA
SS SS
SS SS
A10/AP
SS SS
SS SS
DQ
Hi-z
SS
Hi-z
SS
WE
SS SS
SS SS
DQM
SS SS
SS SS
Self Refresh Entry
Self Refresh Exit
Auto Refresh
:Don't care
*Note : TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs inculding the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays `Low'. Cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
Taiwan Memory Technology, Inc. reserves the right P.28 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A
tm
0 CLOCK CKE
TE CH Auto Refresh Cycle
5 6 0 1 2 3 4 5 6
SS
T431616B
2 3 4 7 8 9 10
Mode Register Set Cycle
1
HIGH
HIGH
SS
SS
CS
*Note2
t RPC SS
RAS
SS
*Note1
SS
CAS
SS
*Note3
ADDR
Key
Key
SS SS
DQ
Hi-z
Hi-z
SS
SS
WE
SS
SS
DQM
SS
MRS
New Command
Auto Refresh
New Command
:Don't care
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Taiwan Memory Technology, Inc. reserves the right P.29 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A
tm
50
TE CH
T431616B
PACKAGE DIMENSIONS 50 LEAD TSOPII (400 mil)
D 26 -HA A2 DEFAULT A
2(4X)
R1
E 1
E
0.21 REF
R2
B
1.5
0.465 REF
A1 -C1 8.78 25 -CDEFAULT A
GAGE 3 (4X)
.2.5
Taiwan Memory Technology, Inc. reserves the right P.30 to change products or specifications without notice.
291 (ZD) -Ce
PLANE
1
L L1
B
"A"
b WITH PLATING
0.10 C b SETING PLANE
BASE METAL
C1
C
SECTION B-B
b1
Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 e R1 R2 1 2 3
Dimension in mm Nom Max 1.20 0.10 0.15 1.00 1.05 0.45 0.35 0.40 0.21 0.127 0.16 20.95 21.08 0.875 REF 11.56 11.76 11.96 10.03 10.16 10.29 0.40 0.50 0.60 0.80 REF 0.80 BSC 0.12 0.12 0.25 0 8 0 10 15 20 10 15 20 Min 0.05 0.95 0.30 0.30 0.12 0.10 20.82
Min 0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394 0.016
0.005 0.005 0 0 10 10
Dimension in inch Nom 0.004 0.039 0.014 0.005 0.825 0.034 REF 0.463 0.400 0.020 0.031 REF 0.031 BSC 15 15
Max 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.830 0.471 0.405 0.024
0.010 8 20 20
Publication Date: JUL. 2001 Revision:A
tm
TE CH
T431616B
PACKAGE DIMENSIONS 60-pin CSP
TOP VIEW
A1 CORNER
A1 CORNER
BOTTOM VIEW
R P N ML K J H GF E D C B A
C
A B CD E F GH J KLMN P R 1 2 3 4 5 6 7
D1 B1
1 2 3 4 5 6 7
A
B D
C1
E3 E2
A1
E
E1
SEATING PLANE
Symbol A A1 B B1 C C1 D D1 E E1 E2 E3
Min 6.30 10.00 0.35 0.35 0.22 0.42
Dimension in mm Nom 6.40 10.10 3.90(typ) 9.10(typ) 0.65(typ) 0.65(typ) 0.4 0.4 0.27 0.21 0.45
Max 6.50 10.20 0.45 0.45 0.32 1.00 0.48
Min 0.248 0.394 0.014 0.014 0.009 0.017
Dimension in inch Nom 2.52 0.398 0.154(typ) 0.358(typ) 0.026(typ) 0.026(typ) 0.016 0.016 0.11 0.008 0.018
Max 2.56 0.402 0.018 0.018 0.13 0.039 0.019
Taiwan Memory Technology, Inc. reserves the right P.31 to change products or specifications without notice.
Publication Date: JUL. 2001 Revision:A

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